Clock Constraints in UML/MARTE CCSL
نویسندگان
چکیده
The UML Pro le for Modeling and Analysis of Real-Time and Embedded (RTE) systems has recently been adopted by the OMG. Its Time Model extends the informal and simplistic Simple Time package proposed by UML2 and o ers a broad range of capabilities required to model RTE systems including both discrete/dense and chronometric/logical time. MARTE OMG speci cation introduces a Time Structure inspired from Time models of the concurrency theory and proposes a new clock constraint speci cation language (CCSL) to specify, within the context of UML, usual logical and chronometric time constraints. This paper presents, for the rst time, the formal semantics of some representative CCSL clock constraints concerning logical discrete time. Considering the Time Structure as a concurrent system, we propose a dynamic interpretation to build acceptable solutions that fully respect the constraints. An unusual example about processing Easter days illustrates the use of CCSL and the construction of solutions. Key-words: Time Model, UML/MARTE, logical time ∗ Université de Nice Sophia Antipolis Constraintes d'Horloges de UML/MARTE CCSL Résumé : L'OMG a récemment adopté le pro l UML MARTE pour la Modélisation et l'Analyse de systèmes Temps Réel et Embarqués (TRE). Son modèle de temps étend le paquetage Simple Time de UML2 qui avait l'inconvénient d'être à la fois informel et simpliste. Le modèle de MARTE propose un large spectre de nouvelles possibilités nécessaires pour la modélisation de systèmes temps réel et notamment il prend en compte le temps discret et dense, le temps logique et chronométrique. La spéci cation OMG de MARTE est très volumineuse et n'o rait pas le cadre idéal pour une spéci cation formelle. Elle dé nit une structure de temps inspirée de modèles issus de la théorie de la concurrence. Elle propose également un langage de spéci cation de contraintes d'horloges (CCSL) pour spéci er les contraintes de temps usuelles du domaine, contraintes qui utilisent à la fois le temps logique et chronométrique. La spéci cation montre aussi comment intégrer ces contraintes dans un modèle UML existant. Ce papier présente pour la première fois la sémantique formelle d'une sélection de contraintes d'horloge o ertes par CCSL. Cette sélection ne concerne que du temps discret et logique, mais est toutefois représentative de la diversité des contraintes proposées. Le papier considère la structure de temps de MARTE comme un système concurrent et propose une interprétation dynamique de ce système pour calculer des solutions acceptables, c'est-à-dire qui respectent toutes les contraintes. Un exemple original, qui calcule la date de Pâques, est utilisé pour illustrer la puissance du langage CCSL et la construction dynamique de solutions acceptables. illustrates the use of CCSL and the construction of solutions. Mots-clés : Modèle de Temps, UML/MARTE, temps logique Clock Constraints in UML/MARTE 3
منابع مشابه
Syntax and Semantics of the Clock Constraint Specification Language (CCSL)
The UML Pro le for Modeling and Analysis of Real-Time and Embedded (MARTE) systems has recently been adopted by the OMG. Its Time Model extends the informal and simplistic Simple Time package proposed by UML2 and o ers a broad range of capabilities required to model real-time systems. The MARTE OMG speci cation introduces a Time Structure inspired from Time models of the concurrency theory and ...
متن کاملVerification of clock constraints: CCSL Observers in Esterel
The Clock Constraint Speci cation Language (ccsl) has been informally introduced in the speci cations of the uml Pro le for Modeling and Analysis of Real-Time and Embedded systems (MARTE). In a previous report entitled Syntax and Semantics of the Clock Constraint Speci cation Language , we equipped a kernel of ccsl with an operational semantics. In the present report we pursue this clari cation...
متن کاملUML Profile for MARTE: Time Model and CCSL
This 90 minutes tutorial gives a basic introduction to the UML Profile for MARTE (Modeling and Analysis of Real-Time and Embedded systems) adopted by the Object Management Group. After a brief introduction to the UML profiling mechanism, we give a broad overview of the MARTE Profile. Then, the tutorial shall focus on the time model of MARTE and its companion language CCSL (Clock Constraint Spec...
متن کاملTowards a Transformation Approach of Timed UML MARTE Specifications for Observer-Based Formal Verification
Modeling timing constraints of distributed systems and multi-clock electronic systems aims to describe different time requirements aspects at a higher abstraction level. An important aspect is the logical time of the behavior of these systems. To model the time requirements, a specification language with multiple clock domains called Clock Constraint Specification Language (CCSL) has been intro...
متن کاملState-based representation of CCSL operators
The UML Pro le for Modeling and Analysis of Real-Time and Embedded systems promises a general modeling framework to design and analyze systems. Lots of works have been published on the modeling capabilities o ered by MARTE, much less on veri cation techniques supported. The Clock Constraint Speci cation Language (CCSL), rst introduced as a companion language for MARTE, was devised to o er a for...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2008